By Manuel F. M. Barros, Jorge M. C. Guilherme, Nuno C. G. Horta (auth.)

The microelectronics marketplace developments current an ever-increasing point of complexity with particular emphasis at the creation of complicated mixed-signal systems-on-chip. Strict fiscal and layout pressures have pushed the advance of recent the right way to automate the analog layout approach. although, and regardless of a few major learn efforts, the basic act of layout on the transistor point remains to be played via the trial and mistake interplay among the clothier and the simulator.

This e-book offers a brand new layout automation technique in keeping with a converted genetic set of rules kernel, with a purpose to increase potency at the analog IC layout cycle. The proposed strategy combines a powerful optimization with nook research, desktop studying options and disbursed processing power in a position to take care of multi-objective and limited optimization difficulties. The ensuing optimization device and the development in layout productiveness is established for the layout of CMOS operational amplifiers.

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The use of compound cells reduces the search space because the number of cells handled during placement is lower and consequently reduces the computation times. Another knowledge-based approach with optimization is given by IPRAIL [40] and LAYGEN [35]-[36] in which the information presented in the template is defined manually or automatically and used to guide the layout generator during the synthesis procedure. The constraints defined in the template reduce the solution space, and allow the designer a higher control of the layout generation unlike the general optimization approaches [35].

The decision rules are introduced by an expert designer or automatically generated by means of a learning process. Another method comprises computing the feasible performance space for each topology within the library and, then compare with the desired performance specs, by AMGIE [2] and [11]. A different method consists of combining the topology selection with the device sizing task and employing an optimization based approach by DARWIN [12] using genetic algorithms. This design mechanism illustrated in Fig.

Alternative tools: VHDL, VHDL-AMS. SUB-ADC DAC 2x GAIN 3. Circuit Level Validation: SPICE like simulators. The requirements for high gain and GBW, with low output impedance and noise leads to a special topology based on telescopic cascade amplifiers followed by a common source stage. These sizes were verified with SPICE and by analytic equations to meet the design constraints. Alternative tools: HSPICE, SPECTRE. 4. System Layout Validation: Assura, Diva. Manual layout was required for the S/H and residue amplifier.

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